1. Field of Invention
The present invention relates to a flash memory structure and its method of manufacture. More particularly, the present invention relates to a flash memory having a split-gate source side injection structure and its method of manufacture.
2. Description of Related Art
Nonvolatile memories are now extensively used in many electronic devices. For example, devices for storing structural data, devices for storing programming data or other intermediate data that needs to be retrieved and stored repetitively all use some form of nonvolatile memory. The most widely used type of programmable nonvolatile memory in personal computers and electronic equipment include the erasable electrical programmable read-only-memories (EEPROMs). A conventional EEPROM is a structure having a floating gate transistor. EEPROM has many advantages, including the capability of writing data into, erase data from or storing data permanently. However, the storage and retrieval rate of a conventional EEPROM is rather slow. Hence, an EEPROM having a faster storage/retrieval rate known as flash memory is developed.
FIG. 1 is a cross-sectional view showing the structure of a conventional flash memory unit. As shown in FIG. 1, the basic component of a conventional flash memory is a floating gate transistor. The floating gate transistor is constructed by forming a tunneling oxide layer 110 over a P-type substrate 100, and then forming a floating gate layer 120 over the tunneling oxide layer 110. A dielectric layer 130 is then formed over the floating gate layer 120. After that, a control gate layer 140 is formed over the dielectric layer 130. Subsequently, N-type drain region 150 and source region 160 are formed in the semiconductor substrate 100 on each side of the floating gate 120. This is followed by forming oxide spacers 170 on the sidewalls of the floating gate 120 and the control gate 140 in order to protect the floating gate transistor. The Fowler-Nordheim tunneling effect is utilized in the operation of a flash memory. When data need to be stored in the flash memory, a high voltage of around 12V is applied between the drain terminal region 150 and the source terminal 160. Similarly, a high voltage is also applied to the control gate 140. Hot electrons flowing out from the source region 160 will tunnel through the tunneling oxide layer 110 near the drain region 150. The injected hot carriers will then be trapped inside the floating gate 120, thereby increasing the threshold voltage of the floating gate transistor and achieving the data storage function. On the other hand, when data need to be erased from the flash memory, a negative voltage of suitable magnitude is applied to the control gate 140. Electrons trapped inside the floating gate 120 will be able to tunnel in a reverse direction through the tunneling oxide layer 110 away from the floating gate 120. Hence, the stored data in the flash memory is erased, and the floating gate transistor returns to its previous state.
The source region and the drain region of the flash memory are located symmetrically on each side of the floating gate with each having an identical diffusion profile of impurities. Therefore, a sufficiently high electric field must be generated in the channel before hot carriers can be injected through the tunneling oxide layer near the drain region and landed inside the floating gate. In other words, a high voltage must be supplied between the drain and source terminal.
In light of the foregoing, there is a need to improve the flash memory structure for increasing programming efficiency.